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Immad attributed lower Chinese AI prices to compute constraints that encouraged efficient model design, distillation, and strong inference engineering, alongside lower research costs and thinner margins. Dave warned that stacked margins at TSMC, Nvidia, and model providers may compress as companies design chips and build fabs themselves.
Intel’s 14A process uses high-NA EUV as an option because backside power frees front-side wiring space, letting Intel print some patterns in one pass. Chris Oth says TSMC’s different wiring constraints make high-NA less useful for its process.
Pushkar Ranade says foundry economics depend heavily on scale: roughly 80% of a fab’s costs are fixed, so utilization and yield gains sharply increase output from the same footprint. He says only three foundries remain at the leading edge, and Intel’s technology gap with TSMC matters less than timely execution and high yields.
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